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A part of the program of the SPC Control Methodology revamp, we need support to analyze and assess the current Control Limits and Out of Control Alarms setup on SPC charts.Apply for position
In LFoundry the Planning team use a Micron S/W (PDM) to elaborate fab capacity scenarios in order to evaluate the feasibility to accept new customer demands.
A capacity scenario computation is based on production data coming from MES (Manufacturing Execution Systems) , like product cycle time, equipment availability, equipment constraints, equipment throughput ,number and mix of products in line.
Since Lfoundry is working to replace the current MES with a new third party software provided by Eyelit , there is the need to reengineering the current planning business
System to either align it to the new third part s/w and to new business needs.
LFoundry is working to replace Manufacturing Execution Systems with a new third party software provided by Eyelit. We should aggregate business requirements elaborating a new logic for data presentation.Apply for position
Optical performances of CMOS imagers can be affected by contamination caused by several elements found, even if in extremely low concentration, in semiconductor production environment.
In particular, contamination by noble elements like, for example, Gold or Silver, is extremely critical since these elements have a very low migration rate in the silicon, so they are not easily segregated into the gettering sites. They remain electrically active, and contribute to the so called “hot pixel” defects.
Unfortunately, the noble elements are also very difficult to be effectively detected by VPD/ICP-MS, the technique traditionally and successfully used to detect most of the other elements (like Fe, Cr, Ni, Na, Ca...).
In fact, the chemical mixtures typically used to dissolve noble metals (like Aqua Regia) are very aggressive to the silicon substrate as well, damaging the wafer surface and making recovery by the automated equipment used for this technique (VPD) very difficult and not reliable.
In order to allow the implementation of routine analysis for the full elemental range of interest, alternative chemistries should be defined (through theoretical modeling and analytical test confirmation), capable to assure acceptable analytical recovery for noble elements and the other common elements at same time.
The Senior Device Modeling Engineer develops the models for the simulation of the device behavior that allow the analog and/or digital designer to verify the functionality of his circuit under different conditions. The main activities of the device modeling engineer are the definition of test structures, the preparation of measurement instructions, the analysis, interpretation and processing of measurement data and the extraction of model parameters and subsequent implementation to the appropriate model structure. The final model has to be prepared fitting the PDK (process design kit) and it has to include all required and available parameters (e.g. Monte Carlo, Mismatch, Noise, Corners, etc…). A high level of quality awareness during the comparison of measurement data versus simulation results and a frequent verification of the actual values in the context of the device specification and EDR (electric design rules) are strongly required. Furthermore the daily business includes the communication and interaction with the process and technology departments, the PDK team and the technical support for customers and IP partners.Apply for position
LFoundry is looking for Equipment Technician profile. The working area of employment is our Semiconductor Manufacturing Fab (Solid State IC Production and Development). People in this position work with the Leaders of the specific engineering and production module (Photolithography/Dry Etch/ Thin Film/Diffusion) and will be involved in some of the activities listed below:
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