LF350 PDK

Process specification

LF350 is a modular 0.35µm RF CMOS process, offering up to 6 levels of Al plus thick metal (2 - 6µm), optionally a MIM capacitor, a polyimide passivation and I/O voltages of 3.3V and 5.0V.

Process Options

 

Core Process Modules
Module Name	Masks	Description
MOS3	15	Standard 3.3V MOS module with single poly, dual metal
MOS5	15	Standard 5.0V MOS module with single poly, dual metal

The following add on modules are actually available.

Addon Process Modules
Module Name	Add. Masks	Description
MOS35	5	3.3V and 5.0V MOS module, one additional gate oxide
M3	2	3 Metal Layers
M4	4	4 Metal Layers
M5	6	5 Metal Layers
M6	8	6 Metal Layers
MIM	1	Metal insulator metal capacitor
NISO	1	N isolation for P WELL, additional NPN parasitic bipolar transistor
PIQ	1	Polyimide passivation

Process Flow

Mask Layers Layer Description DIFF define active area POLY1 used as resistor and in PIP capacitor; future option NISO isolate PWELL, NPN bipolar transistor NWELL common well for PMOS PWELL common well for NMOS P_MVT PMOS threshold adjust for 3.3V N_MVT NMOS threshold adjust for 3.3V MG non-volatile memor; future option CAP future option MVT define 3.3V gate oxide area N_DUALGTE N poly doping POLY2 transistor gates, resistors P_MIN_MVT PMOS extension 3.3V N_MIN_MVT NMOS extension 3.3V

Mask Layers Layer Description P_MIN_HVT PMOS extension 5.0V N_MIN_HVT NMOS extension 5.0V P_PLUS PMOS source/drain N_PLUS NMOS source/drain SALBLOCK salicide block - defines notsalicided area CONT contact to poly and active area METAL1 metalization level 1 MIM1 metal insulator metal capacitor top electrode VIA_F final via METAL_F final metal VIA_T connect METAL_F and METAL_T METAL_T thick metal SIL open passivation PIQ open polyimide IVD open inductor passivation

Device Overview

MOS Transistors

Device	Name	Module	Vt	Ids	BVds	Ioff (typ/max)	Vds/Vgb (max)
			V	µA/µm	V	pA/µm	V
3.3V NMOS	nmos_3	MOS3 or MOS35	0.59	500	10	1/100	3.7
5.0V NMOS	nmos_5	MOS5 or MOS35	0.65	500	10	5/100	6.0
3.3V PMOS	pmos_3	MOS3 or MOS35	-0.54	-380	-7	-2/-70	-3.7
5.0V PMOS	pmos_5	MOS5 or MOS35	-0.66	-340	-8	-10/-100	-6.0

All NMOS devices are also available as isolated devices in Deep NWELL (NISO). Up to now, there is no difference in transistor models between isolated and not isolated devices.

Bipolar Transistors

Device	Name	Module	Vbe	hFE
			V
1.8V NPN	npn	NISO	0.7	40

Capacitors

Device	Name	Module	Area Cap.	Remark
			fF/µm 2
MIM	cmim	MIM	0.98
MOS Cap 3.3V NMOS	ccapn	MOS3 or MOS35	4.8	@ -3.3V, drop 25% at -1.0V
MOS Cap 5.0V NMOS	ccapn_h	MOS5 or MOS35	2.0	@ -5.0V, drop 25% at -1.2V
MOS Cap 3.3V PMOS	ccapp	MOS3 or MOS35	4.9	@ 3.3V, drop 25% at 1.0V

 

Resistors and Conductors

Device	Name	Module	RS	rel. Temp. Coeff.
			Ω/square	10 -3/K
N+poly salicide	rnpoly_s	any core	10	2.8
P+poly salicide	rppoly_s	any core	10	4
P+poly low	rppoly_l	any core	340	-0.15
P+poly high	rppoly_h	any core	2200	-1.75
LTC Poly	rnpoly_lt	any core	135	< 0.02
N+PWELL	rpwell_n	any core	110	1.5
P+NWELL	rnwell_p	any core	175	0.5
NWELL	rnwell	any core	1250	5.5
NWELL + STI	rnwell_s	any core	1900	5.5
PWELL	rpwell	any core	650	3.5
PWELL + STI	rpwell_s	any core	730	5.3
Metal	rmet_1	any core	0.09	3.2
Metal Final	rmet_f	any core	0.04	3

Basic Design Rules

Mask 1	Mask 2	Width [µm]	Spacing [µm]
NWELL		1.5	1.5
Active Area		0.8	0.54
Poly Silicon Gate		0.35	0.53
Poly Silicon Gate	Contact		0.32
Poly Silicon Gate	Active Area		0.32
Contact		0.4	0.4
Metal 1		0.5	0.5
Final Metal		0.58	0.58