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LF150 PDK
Process specification
LF150 is a modular 0.15µm RF CMOS process, offering up to 6 levels of Al plus thick metal (2 - 6µm), optionally a MIM capacitor, a polyimide passivation and I/O voltages of 1.8V, 3.3V and 5.0V.
Process Options
| Core Process Modules | | Module Name | Masks | Description | | MOS18L | 19 | Low leakage 1.8V MOS module with single poly, quad metal | | MOS18S | 19 | Standard 1.8V MOS module with single poly, quad metal | | MOS18SL | 21 | Standard and low leakage 1.8V MOS module with single poly, quad metal | The following add on modules are actually available. | Addon Process Modules | | Module Name | Add. Masks | Description | | MOS3 | 6 | 3.3V MOS module, additional gate oxide | | MOS5 | 5 | 5.0V MOS module, additional gate oxide | | MOS35 | 10 | 3.3V and 5.0V MOS module, two additional gate oxides | | M5 | 2 | 5 Metal Layers | | M6 | 4 | 6 Metal Layers | | MT | 2 | Thick metal (2 - 6µm) | | MIM | 1 | Metal insulator metal capacitor | | NISO | 1 | N isolation for P WELL, additional NPN parasitic bipolar transistor | | PIQ | 1 | Polyimide passivation |
Process Flow
| Mask Layers | | Layer | Description | | DIFF | define active area | | NISO | isolate PWELL, NPN bipolar transistor | | NWELL | common well for PMOS | | PWELL | common well for NMOS | | P_MVT | PMOS threshold adjust for 3.3V | | N_MVT | NMOS threshold adjust for 3.3V | | P_CORE | PMOS standard threshold adjust | | N_CORE | NMOS standard threshold adjust | | P_LOWL | PMOS low leak threshold adjust | | N_LOWL | NMOS low leak threshold adjust | | MVT | define 3.3V gate oxide area | | NO_LVT | define NOT 1.8V gate oxide area | | N_DUALGTE | N poly doping | | HVT | define 16V gate oxide area | | POLY2 | transistor gates, resistors | | P_MIN_LVT | PMOS extension 1.8V | | N_MIN_LVT | NMOS extension 1.8V | | P_MIN_MVT | PMOS extension 3.3V | | N_MIN_MVT | NMOS extension 3.3V | | P_MIN_HVT | PMOS extension 5.0V | | N_MIN_HVT | NMOS extension 5.0V | | | Mask Layers | | Layer | Description | | P_PLUS | PMOS source/drain | | N_PLUS | NMOS source/drain | | SALBLOCK | salicide block - defines notsalicided area | | CONT | contact to poly and active area | | METAL1 | metalization level 1 | | VIA1 | connect metal 1 and metal 2 | | METAL2 | metalization level 2 | | VIA2 | connect metal 2 and metal 3 | | METAL3 | metalization level 3 | | VIA3 | connect metal 3 and metal 4 | | METAL4 | metalization level 4 | | VIA4 | connect metal 4 and metal 5 | | METAL5 | metalization level 5 | | MIM1 | metal insulator metal capacitor top electrode | | VIA_F | final via | | METAL_F | final metal | | VIA_T | connect METAL_F and METAL_T | | METAL_T | thick metal | | SIL | open passivation | | PIQ | open polyimide | | IVD | open inductor passivation | |
Device Overview
MOS Transistors | Device | Name | Module | Vt | Ids | BVds | Ioff (typ/max) | Vds/Vgb (max) | | | | | V | µA/µm | V | pA/µm | V | | 1.8V NMOS standard | nmos_hs | MOS18S or MOS18SL | 0.58 | 600 | 4 | 5/70 | 2.0 | | 1.8V NMOS low leakage | nmos_ll | MOS18L or MOS18SL | 0.70 | 500 | 4 | 1/3 | 2.0 | | 3.3V NMOS | nmos_3 | MOS3 or MOS35 | 0.58 | 500 | 10 | 1/100 | 3.7 | | 5.0V NMOS | nmos_5 | MOS5 or MOS35 | 0.7 | 400 | 11 | 1/10 | 6.0 | | 1.8V PMOS standard | pmos_hs | MOS18S or MOS18SL | -0.54 | -230 | -5 | -2/-70 | -2.0 | | 1.8V PMOS low leakage | pmos_ll | MOS18L or MOS18SL | -0.67 | -180 | -5 | -0.5/-3 | -2.0 | | 3.3V PMOS | pmos_3 | MOS3 or MOS35 | -0.54 | -380 | -7 | -2/-70 | -3.7 | | 5.0V PMOS | pmos_5 | MOS5 or MOS35 | -0.7 | -270 | -10 | -1/-10 | -6.0 | All NMOS devices are also available as isolated devices in Deep NWELL (NISO). Up to now, there is no difference in transistor models between isolated and not isolated devices.
Bipolar Transistors | Device | Name | Module | Vbe | hFE | | | | | V | | | 3.3V NPN | npn | NISO; MOS3 or MOS35 | 0.67 | 35 | | 3.3V PNP | pnp | MOS3 or MOS35 | -0.66 | 21 |
Capacitors | Device | Name | Module | Area Cap. | Remark | | | | | fF/µm 2 | | | MIM | cmim | MIM | 0.98 | | | MOS Cap 1.8V NMOS | ccapn_l | any Core | 9.4 | @ -1.8V, drop 25% at -1.1V | | MOS Cap 3.3V NMOS | ccapn | MOS3 or MOS35 | 4.8 | @ -3.3V, drop 25% at -1.0V | | MOS Cap 5.0V NMOS | ccapn_h | MOS5 or MOS35 | 2.0 | @ -5.0V, drop 25% at -1.2V | | MOS Cap 3.3V PMOS | ccapp | MOS3 or MOS35 | 4.9 | @ 3.3V, drop 25% at 1.0V |
Resistors and Conductors | Device | Name | Module | RS | rel. Temp. Coeff. | | | | | Ω/square | 10 -3/K | | N+poly salicide | rnpoly_s | any core | 10 | 2.8 | | P+poly salicide | rppoly_s | any core | 10 | 4 | | P+poly low | rppoly_l | any core | 340 | -0.15 | | P+poly high | rppoly_h | any core | 2200 | -1.75 | | LTC Poly | rnpoly_lt | any core | 135 | < 0.02 | | N+PWELL | rpwell_n | any core | 110 | 1.5 | | P+NWELL | rnwell_p | any core | 175 | 0.5 | | NWELL | rnwell | any core | 1250 | 5.5 | | NWELL + STI | rnwell_s | any core | 1900 | 5.5 | | Metal | rmet_1 ... rmet_5 | any core | 0.08 | 3.2 | | Metal Final | rmet_f | any core | 0.04 | 3 |
Basic Design Rules | Mask 1 | Mask 2 | Width [µm] | Spacing [µm] | | NWELL | | 1.5 | 1.5 | | Active Area | | 0.32 | 0.32 | | Poly Silicon Gate | | 0.15 | 0.26 | | Poly Silicon Gate | Contact | | 0.12 | | Poly Silicon Gate | Active Area | | 0.14 | | Contact | | 0.18 | 0.3 | | Metal 1/2/3/4/5 | | 0.24 | 0.24 | | Via 1/2/3/4 | | 0.24 | 0.24 | | Final Metal | | 0.58 | 0.58 | | Final Via | | 0.24 | 0.24 |
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