In your new role you will be responsible to create and verify layouts of
analog circuits, blocks and IPs using our LFoundry CMOS technology nodes.
List of main activities:
·Layout and verification of IPs (e.g. IOs, PA, PLL, etc.) test chips and
test products
·Working closely with the design team and other R&D teams regarding layout
requirements and implementation
·Using scripting languages (e.g. SKILL, Python, etc.) to generate layout
in a semi-automated way
·Using version control tools to manage project data
Your likely skills and knowledge:
·Technician, Bachelor or Master Degree in a technical field
·Minimum of 2 years’ experience in custom CMOS analog layout of circuits
and blocks
·Understanding of layout approaches and techniques (e.g. matching, minimizing
parasites, ESD, etc.)
·Fundamental understanding of analog and mixed-signal design flows
methodologies
·Strong experience in design and verification tools like Cadence
Virtuoso, Assura, QRC, Calibre DRC/LVS, etc.
·Strong organizational skills, to manage multiple tasks simultaneously
and know how to set priorities according to requirements
·Good communication skills and team player